`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:31:09 04/28/2014 
// Design Name: 
// Module Name:    Frame1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Frame3(
	output 		reg	[7:0] 	color,		
	input					[10:0]	hcounter, vcounter,										
	input 				clk , clk_5Hz, blank
//	input			RESUME, RESTART, QUIT
				);
	
	parameter	PAUSEh=257, PAUSEv=120,	
					RESUMEh=243, RESUMEv=180,	
					RESTARTh=237, RESTARTv=240,	
					QUITh=269, QUITv=300;

					
	
	reg	[2:0]		cc;				
	reg	[1:0]		f;
	reg 	[15:0]	addr;
	
	wire				data;
	
	
	always@(posedge clk_5Hz)										
			begin 
				if(f<3)
					f<=f+1;
				else					
					f<=0;
			end		
		
	
			
	F_ROM_3 U3(clk ,addr, data);	
	
	always@(hcounter, vcounter)
		begin 
			if (blank==0)
				begin
////////////////////////////////PAUSE////////////////////////////////////				
					if (((hcounter-PAUSEh)<126)&&((hcounter-PAUSEh)>=0)&&((vcounter-PAUSEv)<30)&&((vcounter-PAUSEv)>=0))
						begin
							cc<=3'b000;
							addr<=(vcounter-PAUSEv)*126+hcounter-PAUSEh;
						end	
////////////////////////////////RESUME//////////////////////////////////				
					else if (((hcounter-RESUMEh)<154)&&((hcounter-RESUMEh)>=0)&&((vcounter-RESUMEv)<30)&&((vcounter-RESUMEv)>=0))
						begin
//							if (RESUME)
								if (f<2)
									begin
										cc<=3'b001;
										addr<=(vcounter-RESUMEv)*154+hcounter-RESUMEh+3780;
									end
								else 
									begin
										cc<=3'b010;
										addr<=(vcounter-RESUMEv)*154+hcounter-RESUMEh+3780;
									end
//								else 
//									begin
//										cc<=3'b001;
//										addr<=(vcounter-RESUMEv)*154+hcounter-RESUMEh+3780;
//									end
							end
////////////////////////////////RESTART////////////////////////////////							
					else if (((hcounter-RESTARTh)<169)&&((hcounter-RESTARTh)>=0)&&((vcounter-RESTARTv)<30)&&((vcounter-RESTARTv)>=0))
						begin
//							if (RESTART)
								if (f<2)
									begin
										cc<=3'b011;
										addr<=(vcounter-RESTARTv)*169+hcounter-RESTARTh+8400;
									end
								else 
									begin
										cc<=3'b010;
										addr<=(vcounter-RESTARTv)*169+hcounter-RESTARTh+8400;
									end
//								else 
//									begin
//										cc<=3'b011;
//										addr<=(vcounter-RESTARTv)*169+hcounter-RESTARTh+8400;
//									end
							end
////////////////////////////////QUIT////////////////////////////////////					
					else if (((hcounter-QUITh)<103)&&((hcounter-QUITh)>=0)&&((vcounter-QUITv)<30)&&((vcounter-QUITv)>=0))
						begin
//							if (QUIT)
								if (f<2)
									begin
										cc<=3'b100;
										addr<=(vcounter-QUITv)*103+hcounter-QUITh+13470;
									end
								else 
									begin
										cc<=3'b010;
										addr<=(vcounter-QUITv)*103+hcounter-QUITh+13470;
									end
//								else 
//									begin
//										cc<=3'b100;
//										addr<=(vcounter-QUITv)*103+hcounter-QUITh+13470;
//									end
							end
/////////////////////////////////////////////////////////////////////////	
					else 
						begin
							addr<=0;
						end	
				end
			else
				begin
					addr<=0;
				end
		end
		
		always@(posedge clk)		
			begin
				case (cc)
				3'b000:	
					begin
						color<=data?8'b00000000:8'b11111001;	//PAUSE color
					end
				3'b001:	
					begin
						color<=data?8'b00000000:8'b01111111;	//RESUME color
					end
				3'b010:	
					begin
						color<=data?8'b00000000:8'b11111100;	//BLINK color
					end
				3'b011:	
					begin
						color<=data?8'b00000000:8'b11111110;	//RESTART color
					end
				3'b100:	
					begin
						color<=data?8'b00000000:8'b10010111;	//RESTART color
					end
				default: color<=8'b00000000;
				endcase
			end	
endmodule

